Issued Patents All Time
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8209562 | Double data rate converter circuit includes a delay locked loop for providing the plurality of clock phase signals | Oswald Becca, Peter Nyasulu | 2012-06-26 |
| 7661010 | Apparatus and method for interfacing to a memory | Oswald Becca, Peter Nyasulu | 2010-02-09 |
| 6087875 | Single-edge adjustable delay circuit | — | 2000-07-11 |