Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10707389 | Light emitting device | Hiroki YUU, Toshiaki Moriwaki | 2020-07-07 |
| 10224468 | Method of manufacturing light emitting device | Hiroki YUU, Toshiaki Moriwaki | 2019-03-05 |
| 9917234 | Method of manufacturing light emitting device | Hiroki YUU, Toshiaki Moriwaki | 2018-03-13 |
| 9368675 | Method of manufacturing light-emitting device and wiring substrate for light-emitting element | Yoshikazu Takeuchi, Toshiaki Moriwaki, Atsushi Takeichi | 2016-06-14 |
| 9190585 | Light emitting device and lighting equipment | Hiroto Tamaki, Eiko MINATO | 2015-11-17 |
| 6813598 | Logic simulation method and logic simulation apparatus | — | 2004-11-02 |
| 5931963 | Fault simulation apparatus | — | 1999-08-03 |
| 5828673 | Logical check apparatus and method for semiconductor circuits and storage medium storing logical check program for semiconductor circuits | Yukiharu Mikawa, Tadateru Kamimizo | 1998-10-27 |
| 5706223 | Logic simulator and logic simulation method | — | 1998-01-06 |
| 5701254 | Switch level simulation system | — | 1997-12-23 |
| 5677856 | Simulation apparatus for circuit verification | — | 1997-10-14 |
| 5471409 | Logic simulation apparatus and circuit simulation apparatus | — | 1995-11-28 |
| 5396615 | System for simulating electrical delay characteristics of logic circuits | — | 1995-03-07 |
| 5345401 | Logic circuit simulator for verifying circuit operations having MOS transistors | — | 1994-09-06 |
| 5202841 | Layout pattern verification system | — | 1993-04-13 |