Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6853030 | Semiconductor device including multiple field effect transistors, with first FETs having oxide spacers and the second FETs having oxide nitride oxidation protection | Motoshige Igarashi, Keiichi Yamada, Katsuya Okada, Keiichi Higashitani | 2005-02-08 |
| 6657247 | Semiconductor device with MIM capacitance element | Kiyoaki Morita | 2003-12-02 |
| 6620666 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE OF DUAL-GATE CONSTRUCTION, AND SEMICONDUCTOR DEVICE MANUFACTURED THEREBY INCLUDING FORMING A REGION OF OVER-LAPPING N-TYPE AND P-TYPE IMPURITIES WITH LOWER RESISTANCE | Keiichi Higashitani, Masao Sugiyama | 2003-09-16 |
| 6614643 | Semiconductor device having a capacitor element | Kiyoaki Morita | 2003-09-02 |
| 6541823 | Semiconductor device including multiple field effect transistors and manufacturing method thereof | Motoshige Igarashi, Keiichi Yamada, Katsuya Okada, Keiichi Higashitani | 2003-04-01 |
| 6486558 | Semiconductor device having a dummy pattern | Masao Sugiyama | 2002-11-26 |
| 6479873 | Semiconductor device with self-aligned contact structure | Keiichi Higashitani | 2002-11-12 |
| 6064099 | Layout of well contacts and source contacts of a semiconductor device | Keiichi Yamada, Atsushi Maeda, Keiichi Higashitani | 2000-05-16 |