Issued Patents All Time
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8291364 | Automated digital circuit design tool that reduces or eliminates adverse timing constraints do to an inherent clock signal skew, and applications thereof | Soumya Banerjee, Thomas Stephen Chanak, Jr. | 2012-10-16 |
| 7917882 | Automated digital circuit design tool that reduces or eliminates adverse timing constraints due to an inherent clock signal skew, and applications thereof | Soumya Banerjee, Thomas Stephen Chanak, Jr. | 2011-03-29 |