Issued Patents All Time
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12033687 | Computer memory systems employing localized generation of global bit line (GBL) clock signal to reduce clock signal read path divergence for improved signal tracking, and related methods | Rajesh Kumar | 2024-07-09 |
| 11948624 | Memory bit cell array including contention-free column reset circuit, and related methods | Rajesh Kumar | 2024-04-02 |
| 11581036 | Searchable array circuits with load-matched signals for reduced hit signal timing margins and related methods | Rajesh Kumar | 2023-02-14 |