Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12073868 | Timing adjustment for data input/output buffer circuits | — | 2024-08-27 |
| 12068021 | Low power clock injection during idle mode operations | Takayuki Miyamoto, Kallol Mazumder, Scott E. Smith | 2024-08-20 |
| 11403617 | Wallet system and non-transitory storage medium | Nozomu YOSHIOKA, Yuzo Yamada, Tsukasa KARASAWA, Yusuke Tomimoto | 2022-08-02 |
| 10504582 | Timing control circuit shared by a plurality of banks | — | 2019-12-10 |
| 10332584 | Semiconductor device including subword driver circuit | — | 2019-06-25 |
| 10229730 | Timing control circuit shared by a plurality of banks | — | 2019-03-12 |
| 9779800 | Timing control circuit shared by a plurality of banks | — | 2017-10-03 |
| 9666306 | Semiconductor device having hierarchically structured bit lines | — | 2017-05-30 |
| 9552866 | Semiconductor device including subword driver circuit | — | 2017-01-24 |
| 9236149 | Semiconductor device having hierarchically structured bit lines | — | 2016-01-12 |
| 9208851 | Semiconductor device and data processing system | — | 2015-12-08 |
| 9019787 | Semiconductor device having hierarchical bit line structure | Yasuhiro Matsumoto, Takeshi Ohgami, Daiki Izawa | 2015-04-28 |
| 8693278 | Semiconductor device and data processing system | — | 2014-04-08 |
| 8649233 | Semiconductor device | — | 2014-02-11 |
| 8233344 | Semiconductor device | — | 2012-07-31 |
| 8208324 | Semiconductor memory device that can relief defective address | Kyoichi Nagata | 2012-06-26 |
| 7193915 | Semiconductor memory device | — | 2007-03-20 |
| 7180817 | Semiconductor memory device with column selecting switches in hierarchical structure | — | 2007-02-20 |