Issued Patents All Time
Showing 51–71 of 71 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11238937 | Apparatus for programming memory cells using multi-step programming pulses | — | 2022-02-01 |
| 11217310 | Memory devices with distributed block select for a vertical string driver tile architecture | — | 2022-01-04 |
| 11188473 | Cache release command for cache reads in a memory sub-system | Yoav Weinberg | 2021-11-30 |
| 11043507 | Devices including dummy regions, and related memory devices and electronic systems | — | 2021-06-22 |
| 10910395 | Methods of forming semiconductor device structures | — | 2021-02-02 |
| 10891993 | Wave pipeline | Kaveh Shakeri, Ali Feiz Zarrin Ghalam, Qiang Tang | 2021-01-12 |
| 10802721 | Memory devices configured to latch data for output in response to an edge of a clock signal generated in response to an edge of another clock signal | Qiang Tang, Ali Feiz Zarrin Ghalam, Hoon Choi, Daesik Song | 2020-10-13 |
| 10741252 | Apparatus and methods for programming memory cells using multi-step programming pulses | — | 2020-08-11 |
| 10650895 | Memory devices with distributed block select for a vertical string driver tile architecture | — | 2020-05-12 |
| 10580791 | Semiconductor device structures, semiconductor devices, and electronic systems | — | 2020-03-03 |
| 10453533 | Memory devices with distributed block select for a vertical string driver tile architecture | — | 2019-10-22 |
| 10387048 | Memory devices configured to latch data for output in response to an edge of a clock signal generated in response to an edge of another clock signal | Qiang Tang, Ali Feiz Zarrin Ghalam, Hoon Choi, Daesik Song | 2019-08-20 |
| 10373970 | Semiconductor device structures including staircase structures, and related methods and electronic systems | — | 2019-08-06 |
| 10360956 | Wave pipeline | Kaveh Shakeri, Ali Feiz Zarrin Ghalam, Qiang Tang | 2019-07-23 |
| 10019170 | Controlling timing and edge transition of a delayed clock signal and data latching methods using such a delayed clock signal | Qiang Tang, Ali Feiz Zarrin Ghalam, Hoon Choi, Daesik Song | 2018-07-10 |
| 9710182 | Apparatuses and methods for a memory die architecture including an interface memory | Dean Nobunaga, Ali Feiz Zarrin Ghalam, Xiaojiang Guo | 2017-07-18 |
| 9478270 | Data paths using a first signal to capture data and a second signal to output data and methods for providing data | — | 2016-10-25 |
| 9460803 | Data path with clock-data tracking | Qiang Tang, Ali Feiz Zarrin Ghalam, Hoon Choi, Ramin Ghodsi | 2016-10-04 |
| 9190133 | Apparatuses and methods for a memory die architecture including an interface memory | Dean Nobunaga, Ali Feiz Zarrin Ghalam, Xiaojiang Guo | 2015-11-17 |
| 9183900 | Data paths using a first signal to capture data and a second signal to output data and methods for providing data | — | 2015-11-10 |
| 8937839 | Data paths using a first signal to capture data and a second signal to output data and methods for providing data | — | 2015-01-20 |