| 7139209 |
Zero-enabled fuse-set |
Frank Alejano, Brian J. Ladner, Timothy B. Cowles, Todd A. Merrit, Paul M. Prew |
2006-11-21 |
| 6985393 |
Device for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines |
— |
2006-01-10 |
| 6980478 |
Zero-enabled fuse-set |
Frank Alejano, Brian J. Ladner, Timothy B. Cowles, Todd A. Merritt, Paul M. Prew |
2005-12-27 |
| 6829182 |
Device for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines |
— |
2004-12-07 |
| 6611467 |
Device and method for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines |
— |
2003-08-26 |
| 6442086 |
Device and method for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines |
— |
2002-08-27 |
| 6327201 |
Device and method for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines |
— |
2001-12-04 |
| 6101139 |
Device and method for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines |
— |
2000-08-08 |
| 6002622 |
Device and method for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines |
— |
1999-12-14 |
