Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12114489 | Vertical access line in a folded digitline sense amplifier | — | 2024-10-08 |
| 11264320 | Integrated assemblies | — | 2022-03-01 |
| 9128383 | Sub-resolution assist devices and methods | Fei Wang | 2015-09-08 |
| 8952437 | DRAM cell design with folded digitline sense amplifier | Fei Wang | 2015-02-10 |
| 8736811 | Sub-resolution assist devices and methods | Fei Wang | 2014-05-27 |
| 8716772 | DRAM cell design with folded digitline sense amplifier | Fei Wang | 2014-05-06 |
| 8354317 | Relaxed-pitch method of aligning active area to digit line | — | 2013-01-15 |
| 8183615 | Memory cell with a vertically oriented transistor coupled to a digit line and method of forming the same | — | 2012-05-22 |
| 7961292 | Sub-resolution assist devices and methods | Fei Wang | 2011-06-14 |
| 7915116 | Relaxed-pitch method of aligning active area to digit line | — | 2011-03-29 |
| 7825452 | Memory cell with buried digit line | — | 2010-11-02 |
| 7613025 | Dram cell design with folded digitline architecture and angled active areas | Fei Wang | 2009-11-03 |
| 7541632 | Relaxed-pitch method of aligning active area to digit line | — | 2009-06-02 |
| 7349232 | 6F2 DRAM cell design with 3F-pitch folded digitline sense amplifier | Fei Wang | 2008-03-25 |
| 7271057 | Memory array with overlapping buried digit line and active area and method for forming same | — | 2007-09-18 |
| 7042047 | Memory cell, array, device and system with overlapping buried digit line and active area and method for forming same | — | 2006-05-09 |