| 5944799 |
State machine bus controller providing function and timing parameters to satisfy requirements of asynchronous bus and more than one type of device on the bus |
Charles H. Smoot, Jeffry V. Herring, Jean-Pierre Dupont, Richard Matysiak |
1999-08-31 |
| 5640585 |
State machine bus controller |
Charles H. Smoot, Jeffry V. Herring, Jean-Pierre Dupont, Richard Matysiak |
1997-06-17 |
| 5455930 |
State machine with adaptable timing and state generation mechanisms |
— |
1995-10-03 |
| 5412795 |
State machine having a variable timing mechanism for varying the duration of logical output states of the state machine based on variation in the clock frequency |
— |
1995-05-02 |
| 5269006 |
Method and apparatus for arbitrating access to a microprocessor having real and protected modes |
William F. Dohse, Richard Marcus Mansfield |
1993-12-07 |
| 5220651 |
CPU-bus controller for accomplishing transfer operations between a controller and devices coupled to an input/output bus |
— |
1993-06-15 |
| 5220659 |
System for matching data recovery time between different devices by extending a cycle upon detecting end of cycle |
Jeffry V. Herring |
1993-06-15 |
| 5187779 |
Memory controller with synchronous processor bus and asynchronous I/O bus interfaces |
Joseph M. Jeddeloh, Jeffry V. Herring |
1993-02-16 |
| 5097437 |
Controller with clocking device controlling first and second state machine controller which generate different control signals for different set of devices |
— |
1992-03-17 |
