Issued Patents All Time
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10810337 | Method for modeling glitch of logic gates | Jeff Peng, Jiu-Shang Yang | 2020-10-20 |
| 9298869 | Method for showing hierarchical structure for a given power intent described in a power intent description language with a design described in a hardware design description language, and associated apparatus and associated computer program product | — | 2016-03-29 |