| 9659340 |
Silicon chip of a monolithic construction for use in implementing multiple graphic cores in a graphics processing and display subsystem |
Yoel Shoshan, Guy Sela |
2017-05-23 |
| 9405586 |
Method of dynamic load-balancing within a PC-based computing system employing a multiple GPU-based graphics pipeline architecture supporting multiple modes of GPU parallelization |
— |
2016-08-02 |
| 9082196 |
Application-transparent resolution control by way of command stream interception |
Reuven Bakalash, Yoel Shoshan |
2015-07-14 |
| 8754897 |
Silicon chip of a monolithic construction for use in implementing multiple graphic cores in a graphics processing and display subsystem |
Reuven Bakalash, Efi Fogel |
2014-06-17 |
| 8629877 |
Method of and system for time-division based parallelization of graphics processing units (GPUs) employing a hardware hub with router interfaced between the CPU and the GPUs for the transfer of geometric data and graphics commands and rendered pixel data within the system |
Reuven Bakalash, Gigy Bar-Or, Efi Fogel, Amir Shaham |
2014-01-14 |
| 7843457 |
PC-based computing systems employing a bridge chip having a routing unit for distributing geometrical data and graphics commands to parallelized GPU-driven pipeline cores supported on a plurality of graphics cards and said bridge chip during the running of a graphics application |
Reuven Bakalash, Efi Fogel |
2010-11-30 |
| 7834880 |
Graphics processing and display system employing multiple graphics cores on a silicon chip of monolithic construction |
Reuven Bakalash, Efi Fogel |
2010-11-16 |
| 7812846 |
PC-based computing system employing a silicon chip of monolithic construction having a routing unit, a control unit and a profiling unit for parallelizing the operation of multiple GPU-driven pipeline cores according to the object division mode of parallel operation |
Reuven Bakalash, Efi Fogel |
2010-10-12 |
| 7812844 |
PC-based computing system employing a silicon chip having a routing unit and a control unit for parallelizing multiple GPU-driven pipeline cores according to the object division mode of parallel operation during the running of a graphics application |
Reuven Bakalash, Efi Fogel |
2010-10-12 |
| 7812845 |
PC-based computing system employing a silicon chip implementing parallelized GPU-driven pipelines cores supporting multiple modes of parallelization dynamically controlled while running a graphics application |
Reuven Bakalash, Efi Fogel |
2010-10-12 |
| 7808499 |
PC-based computing system employing parallelized graphics processing units (GPUS) interfaced with the central processing unit (CPU) using a PC bus and a hardware graphics hub having a router |
Reuven Bakalash, Gigy Bar-Or, Efi Fogel, Amir Shaham |
2010-10-05 |
| 7808504 |
PC-based computing system having an integrated graphics subsystem supporting parallel graphics processing operations across a plurality of different graphics processing units (GPUS) from the same or different vendors, in a manner transparent to graphics applications |
Reuven Bakalash, Efi Fogel |
2010-10-05 |
| 7800610 |
PC-based computing system employing a multi-GPU graphics pipeline architecture supporting multiple modes of GPU parallelization dymamically controlled while running a graphics application |
Reuven Bakalash, Gigy Bar-Or, Efi Fogel, Amir Shaham |
2010-09-21 |
| 7800611 |
Graphics hub subsystem for interfacing parallalized graphics processing units (GPUs) with the central processing unit (CPU) of a PC-based computing system having an CPU interface module and a PC bus |
Reuven Bakalash, Gigy Bar-Or, Efi Fogel, Amir Shaham |
2010-09-21 |
| 7800619 |
Method of providing a PC-based computing system with parallel graphics processing capabilities |
Reuven Bakalash, Gigy Bar-Or, Efi Fogel, Amir Shaham |
2010-09-21 |
| 7796129 |
Multi-GPU graphics processing subsystem for installation in a PC-based computing system having a central processing unit (CPU) and a PC bus |
Reuven Bakalash, Gigy Bar-Or, Efi Fogel, Amir Shaham |
2010-09-14 |
| 7796130 |
PC-based computing system employing multiple graphics processing units (GPUS) interfaced with the central processing unit (CPU) using a PC bus and a hardware hub, and parallelized according to the object division mode of parallel operation |
Reuven Bakalash, Gigy Bar-Or, Efi Fogel, Amir Shaham |
2010-09-14 |