Issued Patents All Time
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7606692 | Gate-level netlist reduction for simulating target modules of a design | Stefano Commodaro | 2009-10-20 |
| 7409602 | Methodology for debugging RTL simulations of processor based system on chip | — | 2008-08-05 |