| 7873814 |
Microcode based hardware translator to support a multitude of processors |
Ariel Cohen, Boris Zemlyak |
2011-01-18 |
| 6990567 |
Use of internal general purpose registers of a processor as a Java virtual machine top of stack and dynamic allocation of the registers according to stack status |
Ariel Cohen, Boris Zemlyak |
2006-01-24 |
| 6718539 |
Interrupt handling mechanism in translator from one instruction set to another |
Ariel Cohen, Boris Zemlyak |
2004-04-06 |
| 6691306 |
Use of limited program space of general purpose processor for unlimited sequence of translated instructions |
Ariel Cohen, Boris Zemlyak |
2004-02-10 |
| 6625572 |
Cycle modeling in cycle accurate software simulators of hardware modules for software/software cross-simulation and hardware/software co-simulation |
Boris Zemlyak, Brian Schoner |
2003-09-23 |
| 6564316 |
Method and apparatus for reducing code size by executing no operation instructions that are not explicitly included in code using programmable delay slots |
Bat-Sheva Ovadia, Yael Gross, Eran Briman, Rakefet Freedman |
2003-05-13 |
| 6535900 |
Accumulation saturation by means of feedback |
Yael Gross, Moshe Sheier |
2003-03-18 |
| 6513106 |
Mirror addressing in a DSP |
Winnie K. W. Lau |
2003-01-28 |
| 6407961 |
Dual access memory array |
Yael Gross, Bat-Sheva Ovadia, Avigdor Faians, Eran Briman, Rakefet Freedman +1 more |
2002-06-18 |
| 6188632 |
Dual access memory array |
Yael Gross, Bat-Sheva Ovadia, Avigdor Faians, Eran Briman, Rakefet Freedman +1 more |
2001-02-13 |
| 5537576 |
Expandable memory for a digital signal processor including mapped first and second memory banks forming a continuous and contiguous address space |
Yair Be'ery, Bat-Sheva Ovadia, Yael Gross, Yakov Milstein, Gideon Wertheizer |
1996-07-16 |
| 5463749 |
Simplified cyclical buffer |
Gideon Wertheizer, Yair Be'ery, Bat-Sheva Ovadia, Yael Gross, Yakov Milstein |
1995-10-31 |
