RK

Rajiv Kapur

Lsi Logic: 4 patents #471 of 1,957Top 25%
LS Lsi: 1 patents #914 of 1,740Top 55%
📍 Sunnyvale, CA: #4,767 of 14,302 inventorsTop 35%
🗺 California: #106,790 of 386,348 inventorsTop 30%
Overall (All Time): #1,032,790 of 4,157,543Top 25%
5
Patents All Time

Issued Patents All Time

Showing 1–5 of 5 patents

Patent #TitleCo-InventorsDate
7231370 Method and apparatus for organizational software license sharing 2007-06-12
6725389 Method for minimizing clock skew by relocating a clock buffer until clock skew is within a tolerable limit Alexander Tetelbaum 2004-04-20
6594807 Method for minimizing clock skew for an integrated circuit Alexander Tetelbaum 2003-07-15
6480994 Balanced clock placement for integrated circuits containing megacells Alexander Tetelbaum 2002-11-12
6240542 Poly routing for chip interconnects with minimal impact on chip performance 2001-05-29