MR

Michael D. Rosotker

Lsi Logic: 3 patents #574 of 1,957Top 30%
📍 San Jose, CA: #14,517 of 32,062 inventorsTop 50%
🗺 California: #149,087 of 386,348 inventorsTop 40%
Overall (All Time): #1,655,021 of 4,157,543Top 40%
3
Patents All Time

Issued Patents All Time

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
5340772 Method of increasing the layout efficiency of dies on a wafer and increasing the ratio of I/O area to active area per die 1994-08-23
5341024 Method of increasing the layout efficiency of dies on a wafer, and increasing the ratio of I/O area to active area per die 1994-08-23
5329157 Semiconductor packaging technique yielding increased inner lead count for a given die-receiving area 1994-07-12