DG

Dennis E. Gates

Lsi Logic: 14 patents #102 of 1,957Top 6%
LS Lsi: 3 patents #448 of 1,740Top 30%
Ncr: 2 patents #884 of 2,952Top 30%
SL Symbios Logic: 2 patents #13 of 87Top 15%
TC The Maitland Company: 1 patents #36 of 117Top 35%
AP Avago Technologies General Ip (Singapore) Pte.: 1 patents #883 of 2,004Top 45%
HA Hyundai Electronics America: 1 patents #75 of 148Top 55%
AT AT&T: 1 patents #10,626 of 18,772Top 60%
Overall (All Time): #174,575 of 4,157,543Top 5%
24
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
9110796 Apparatus and circuitry for memory-based collection and verification of data integrity information John R. Kloeppner 2015-08-18
8756371 Methods and apparatus for improved raid parity computation in a storage controller Randy K. Hall, Randolph Sterns, John R. Kloeppner, Mohamad El-Batal 2014-06-17
7913027 Configurable storage array controller John R. Kloeppner, Jeremy Stover, Jason M. Stuhlsatz, Robert E. Stubbs, Mohamad El-Batal 2011-03-22
7562176 Apparatus and methods for clustering multiple independent PCI express hierarchies John R. Kloeppner, Robert E. Stubbs, Mohamad El-Batal, Russell J. Henry, Charles E. Nichols 2009-07-14
7155537 Infiniband isolation bridge merged with architecture of an infiniband translation bridge Bret S. Weber, Russell J. Henry, Keith W. Holt 2006-12-26
7043622 Method and apparatus for handling storage requests Russell J. Henry, Bret S. Weber, John R. Kloeppner, Keith W. Holt 2006-05-09
7035995 Method and apparatus for performing a high speed binary search in time critical environments Russell J. Henry, Bret S. Weber, John R. Kloeppner, Keith W. Holt 2006-04-25
6917990 Method and structure for read prefetch in a storage complex architecture Russell J. Henry, Bret S. Weber, John R. Kloeppner, Keith W. Holt 2005-07-12
6912687 Disk array storage subsystem with parity assist circuit that uses scatter-gather list Rodney A. DeKoning 2005-06-28
6898666 Multiple memory system support through segment assignment Russell J. Henry, Max L. Johnson, Bret S. Weber 2005-05-24
6823472 Shared resource manager for multiprocessor computer system Rodney A. DeKoning, John R. Kloeppner, Keith W. Holt 2004-11-23
6735645 System and method to eliminate race conditions in input/output operations for high bandwidth architectures Bret S. Weber, Russell J. Henry, Keith W. Holt 2004-05-11
6654853 Method of secondary to secondary data transfer with mirroring Scott E. Greenfield 2003-11-25
6385683 Methods and apparatus for raid hardware sequencing to achieve a higher performance raid architecture Rodney A. DeKoning, Keith W. Holt, John R. Kloeppner 2002-05-07
6356969 Methods and apparatus for using interrupt score boarding with intelligent peripheral device Rodney A. DeKoning, Keith W. Holt, John R. Kloeppner 2002-03-12
6216199 Hardware mechanism for managing cache structures in a data storage system Rodney A. DeKoning, John R. Kloeppner 2001-04-10
5959914 Memory controller with error correction memory test application Scott E. Greenfield, Thomas L. Langford, II 1999-09-28
5883909 Method and apparatus for reducing data transfers across a memory bus of a disk array controller Rodney A. DeKoning, Charles Binford 1999-03-16
5734848 Method and appartus for transferring data in a controller having centralized memory John R. Kloeppner, Bret S. Weber 1998-03-31
5634033 Disk array storage system architecture for parity operations simultaneous with other data operations John W. Stewart, Rodney A. DeKoning, Curtis W. Rink 1997-05-27
5012127 Synchronizer circuit with asynchronous clearing Bret S. Weber 1991-04-30
4870616 Compact register set using a psram array Keith B. DuLac 1989-09-26
4866601 Digital data bus architecture for computer disk drive controller Keith B. DuLac 1989-09-12
4268561 Means and method of manufacturing a high strength bar James D. Thompson 1981-05-19