Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7570539 | Method for identifying memory bit cells and connections | — | 2009-08-04 |
| 7299431 | Method for tracing paths within a circuit | — | 2007-11-20 |
| 7003753 | Method of generating a physical netlist for a hierarchical integrated circuit design | — | 2006-02-21 |
| 6854103 | Apparatus and method for visualizing and analyzing resistance networks | — | 2005-02-08 |
| 6539509 | Clock skew insensitive scan chain reordering | — | 2003-03-25 |
| 6272668 | Method for cell swapping to improve pre-layout to post-layout timing | — | 2001-08-07 |
| 5903577 | Method and apparatus for analyzing digital circuits | — | 1999-05-11 |
| 5726997 | Apparatus and method for testing of integrated circuits | — | 1998-03-10 |
| 5528447 | 5-volt tolerant bi-directional i/o pad for 3-volt-optimized integrated circuits | Michael J. McManus, Philip W. Bullinger, Gerald R. Haag, Hoang P. Nguyen | 1996-06-18 |