Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11755753 | Mechanism to enable secure memory sharing between enclaves and I/O adapters | Breno H. Leitao, Mauro Sergio Martins Rodrigues, Daniel Battaiola Kreling | 2023-09-12 |
| 11194724 | Process data caching through iterative feedback | Mauro Sergio Martins Rodrigues, Daniel Battaiola Kreling, Breno H. Leitao | 2021-12-07 |
| 11079940 | Bandwidth management of memory through containers | Daniel Battaiola Kreling, Breno H. Leitao, Mauro Sergio Martins Rodrigues | 2021-08-03 |
| 10936330 | Instantaneous boot of virtual machine instances via remote direct memory access | Daniel Battaiola Kreling, Breno H. Leitao, Mauro Sergio Martins Rodrigues | 2021-03-02 |
| 10824453 | Hypervisor-based just-in-time compilation | Plinio A. S. Freire, Breno H. Leitao | 2020-11-03 |
| 10754776 | Cache balance when using hardware transactional memory | Daniel Battaiola Kreling, Breno H. Leitao, Mauro Sergio Martins Rodrigues | 2020-08-25 |
| 10635605 | Shared memory inter-enclave communication | Breno H. Leitao, Mauro Sergio Martins Rodrigues, Daniel Battaiola Kreling | 2020-04-28 |
| 10467141 | Process data caching through iterative feedback | Mauro Sergio Martins Rodrigues, Daniel Battaiola Kreling, Breno H. Leitao | 2019-11-05 |
| 10338824 | Bandwidth management of memory through containers | Daniel Battaiola Kreling, Breno H. Leitao, Mauro Sergio Martins Rodrigues | 2019-07-02 |
| 10108442 | Optimization and affinity for hypervisor-based just-in-time translator | Plinio A. S. Freire, Breno H. Leitao | 2018-10-23 |