Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10878168 | Method for performing a layout versus schematic test for a multi-technology module | Matthew Thomas Ozalas, Anne Marie Hawkins, Rameshwar Singh | 2020-12-29 |
| 9147034 | Circuit layout verification method | Anne Marie Hawkins | 2015-09-29 |