Issued Patents All Time
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5309371 | Method of and apparatus for designing circuit block layout in integrated circuit | Hiromi Shikata, Yoshito Muraishi, Shoichi Moriya | 1994-05-03 |
| 5187556 | CMOS master slice | Masaaki Nariishi, Noboru Yamakawa, Osamu Ohba | 1993-02-16 |