Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11923015 | Semiconductor storage device and data erasing method | Shinichi Oosera, Sumito Ohtsuki, Yuki Soh | 2024-03-05 |
| 10803950 | Memory device and memory controller | Yasuhiro Shimura, Sumito Ohtsuki, Junichi Kijima, Keisuke Yonehama, Shinichi Oosera +3 more | 2020-10-13 |
| 10347338 | Memory device and memory controller | Yasuhiro Shimura, Sumito Ohtsuki, Junichi Kijima, Keisuke Yonehama, Shinichi Oosera +3 more | 2019-07-09 |
| 10255979 | Semiconductor memory device | Yasuhiro Shimura, Shinichi Oosera, Junichi Kijima, Sumito Ohtsuki, Tomohiro Oda +1 more | 2019-04-09 |
| 8804427 | Nonvolatile semiconductor memory device | Hitoshi Iwai, Shinichi Oosera | 2014-08-12 |
| 8750017 | Resistance-change memory | Mizuki Kaneko, Tomonori Kurosawa | 2014-06-10 |
| 8659947 | Nonvolatile semiconductor memory device | Hitoshi Iwai, Shinichi Oosera | 2014-02-25 |
| 8493796 | Nonvolatile semiconductor memory device | Kazumi Tanimoto | 2013-07-23 |
| 7893478 | Semiconductor storage device and driving method thereof | Takashi Ohsawa, Ryo Fukuda | 2011-02-22 |
| 7839699 | Semiconductor memory device | Takashi Ohsawa | 2010-11-23 |
| 7839711 | Semiconductor memory device and driving method thereof | Takashi Ohsawa | 2010-11-23 |
| 7583538 | Semiconductor memory and read method of the same | Mutsuo Morikado | 2009-09-01 |
| 7463541 | Semiconductor storage device | Takashi Ohsawa | 2008-12-09 |
| 7411850 | Semiconductor storage device | Takashi Ohsawa | 2008-08-12 |
| 7139216 | Semiconductor storage device having a counter cell array to store occurrence of activation of word lines | Takashi Ohsawa | 2006-11-21 |
| 7126843 | Semiconductor memory device using magnetoresistive effect | — | 2006-10-24 |
| 7095652 | Semiconductor storage device | Takashi Ohsawa | 2006-08-22 |
| 6912152 | Magnetic random access memory | Yoshihisa Iwata | 2005-06-28 |
| 6891748 | MRAM having memory cell array in which cross-point memory cells are arranged by hierarchical bit line scheme and data read method thereof | Kenji Tsuchida, Yoshihisa Iwata | 2005-05-10 |
| 6862210 | Magnetic random access memory for storing information utilizing magneto-resistive effects | Kenji Tsuchida, Yoshihisa Iwata | 2005-03-01 |
| 6839269 | Magnetic random access memory | Yoshihisa Iwata | 2005-01-04 |
| 6724653 | Magnetic random access memory | Yoshihisa Iwata | 2004-04-20 |
| 6310806 | Semiconductor memory device with redundant circuit | Hiroaki Nakano | 2001-10-30 |
| 5825712 | Semiconductor integrated circuit | Hiroyuki Noji | 1998-10-20 |