Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5634061 | Instruction decoder utilizing a low power PLA that powers up both AND and OR planes only when successful instruction fetch signal is provided | Atsushi Horie | 1997-05-27 |
| 5452428 | Processor having different operand source information temporarily stored in plural holding registers to avoid using microprogram ROM capacity for such information | Miyuki Nagata | 1995-09-19 |
| 5287483 | Prefetched operand storing system for an information processor | — | 1994-02-15 |
| 4931925 | High speed byte data rearranging processor | Tohru Sasaki | 1990-06-05 |
| 4901236 | Pipeline controlling system to increase effective address calculation performance | — | 1990-02-13 |