Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10871901 | Memory system | Yoshihisa Kojima, Tokumasa Hara, Hiroyuki Moro, Yohei Hasegawa, Yoshiki Saito | 2020-12-22 |
| 10180795 | Memory system utilizing a page buffer for prioritizing a subsequent read request over a pending write | Yoshihisa Kojima, Tokumasa Hara, Hiroyuki Moro, Yohei Hasegawa, Yoshiki Saito | 2019-01-15 |
| 9891837 | Memory system | Yoshihisa Kojima, Tokumasa Hara, Hiroyuki Moro, Yohei Hasegawa, Yoshiki Saito | 2018-02-13 |
| 9792989 | Memory system including nonvolatile memory | — | 2017-10-17 |
| 9264070 | Memory controller, memory system, and memory write method | Akira Yamaga | 2016-02-16 |
| 8843687 | Semiconductor device controlling outbound and inbound path switching sections based on a setting state and controlling method thereof | Hisae Kita | 2014-09-23 |
| 8335264 | Image information transmission apparatus | — | 2012-12-18 |
| 8155204 | Image decoding apparatus and image decoding method | Shuji Michinaka, Kiwamu Watanabe, Masashi Jobashi, Takaya Ogawa, Hiromitsu Nakayama +3 more | 2012-04-10 |
| 8023565 | Picture processing apparatus, semiconductor integrated circuit, and method for controlling a picture memory | Akihiro Oue, Kunihiko Yahagi, Shuji Michinaka, Satoshi Takekawa, Kiwamu Watanabe | 2011-09-20 |
| 7602319 | Image decoding apparatus and decoding method | Shuji Michinaka, Kiwamu Watanabe, Satoshi Takekawa, Masashi Jobashi, Hiromitsu Nakayama +3 more | 2009-10-13 |
| 7586426 | Image coding apparatus and method thereof | Kiwamu Watanabe, Shuji Michinaka, Hiromitsu Nakayama, Yoshinori Shigeta, Satoshi Takekawa +3 more | 2009-09-08 |
| 7567189 | Variable length code decoding apparatus and variable length code decoding method | Takaya Ogawa, Masashi Jobashi, Kiwamu Watanabe, Satoshi Takekawa, Hiromitsu Nakayama +3 more | 2009-07-28 |
| 7102550 | System and method for decoding a variable-length codeword while updating the variable-length codeword | Kiwamu Watanabe, Shuji Michinaka, Akihiro Oue, Satoshi Takekawa | 2006-09-05 |
| 7058867 | Logic circuit and methods for designing and testing the same | — | 2006-06-06 |