Issued Patents All Time
Showing 26–50 of 72 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5892706 | Fram, fram card, and card system using the same | Mitsuru Shimizu | 1999-04-06 |
| 5875129 | Nonvolatile semiconductor memory device including potential generating circuit | Shigeru Atsumi | 1999-02-23 |
| 5812459 | Nonvolatile semiconductor memory device having row decoder supplying a negative potential to wordlines during erase mode | Shigeru Atsumi | 1998-09-22 |
| 5798964 | FRAM, FRAM card, and card system using the same | Mitsuru Shimizu | 1998-08-25 |
| 5729395 | Video tape recorder with liquid crystal display projector having a head drum with fins | — | 1998-03-17 |
| 5715351 | Double deck video cassette tape recorder with video signal processing circuit | — | 1998-02-03 |
| 5680349 | Nonvolatile semiconductor memory device having row decoder supplying a negative potential to word lines during erase mode | Shigeru Atsumi | 1997-10-21 |
| 5600592 | Nonvolatile semiconductor memory device having a word line to which a negative voltage is applied | Shigeru Atsumi | 1997-02-04 |
| 5559737 | Nonvolatile semiconductor memory capable of simultaneously equalizing bit lines and sense lines | Shigeru Atsumi, Masao Kuriyama | 1996-09-24 |
| 5513146 | Nonvolatile semiconductor memory device having a row decoder supplying a negative potential to word lines during erase mode | Shigeru Atsumi | 1996-04-30 |
| 5461437 | Video tape recorder equipped with liquid crystal display projector | Yeong J. Joo | 1995-10-24 |
| 5438542 | Nonvolatile semiconductor memory device | Shigeru Atsumi | 1995-08-01 |
| 5392253 | Nonvolatile semiconductor memory device having row decoder supplying a negative potential to word lines during erase mode | Shigeru Atsumi | 1995-02-21 |
| 5388084 | Non-volatile semiconductor memory device with high voltage generator | Yasuo Itoh, Junichi Miyamoto, Hiroshi Nakamura, Yoshihisa Iwata, Kenichi Imamiya +1 more | 1995-02-07 |
| 5331597 | Semiconductor nonvolatile memory apparatus including threshold voltage shift circuitry | — | 1994-07-19 |
| 5327392 | Semiconductor integrated circuit capable of preventing occurrence of erroneous operation due to noise | Nobuaki Ohtsuka | 1994-07-05 |
| 5296801 | Bias voltage generating circuit | Nobuaki Ohtsuka, Masao Kuriyama | 1994-03-22 |
| 5265061 | Apparatus for preventing glitch for semiconductor non-volatile memory device | — | 1993-11-23 |
| 5237534 | Data sense circuit for a semiconductor nonvolatile memory device | Toshiyuki Sanko | 1993-08-17 |
| 5233566 | Address detector of a redundancy memory cell | Keniti Imamiya, Shigeru Atsumi | 1993-08-03 |
| 5229963 | Semiconductor nonvolatile memory device for controlling the potentials on bit lines | Nobuaki Ohtsuka, Junichi Miyamoto, Shigeru Atsumi | 1993-07-20 |
| 5105385 | Cell array pattern layout for EEPROM device | Nobuaki Ohtsuka, Junichi Miyamoto, Shigeru Atsumi | 1992-04-14 |
| 5046048 | Semiconductor integrated circuit including output buffer | Shigeru Atsumi, Junichi Miyamoto, Nobuaki Ohtsuka, Keniti Imamiya | 1991-09-03 |
| 4974206 | Nonvolatile semiconductor memory device having reference potential generating circuit | Yumiko Iyama, Junichi Miyamoto, Nobuaki Ohtsuka | 1990-11-27 |
| 4970691 | 2-cell/1-bit type EPROM | Shigeru Atsumi, Junichi Miyamoto | 1990-11-13 |