Issued Patents All Time
Showing 76–100 of 126 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5986935 | Semiconductor memory device with high voltage generation circuit | Yumiko Iyama, Hironori Banba | 1999-11-16 |
| 5963500 | Semiconductor memory device | Tadayuki Taura, Hironori Banba | 1999-10-05 |
| 5940322 | Constant voltage generating circuit with improved line voltage control | — | 1999-08-17 |
| 5909406 | Semiconductor memory device | Tadayuki Taura, Akira Umezawa | 1999-06-01 |
| 5901083 | Nonvolatile semiconductor memory device | Hironori Banba | 1999-05-04 |
| 5898335 | High voltage generator circuit | Junichi Miyamoto, Yasuo Itoh | 1999-04-27 |
| 5875129 | Nonvolatile semiconductor memory device including potential generating circuit | Sumio Tanaka | 1999-02-23 |
| 5812459 | Nonvolatile semiconductor memory device having row decoder supplying a negative potential to wordlines during erase mode | Sumio Tanaka | 1998-09-22 |
| 5680349 | Nonvolatile semiconductor memory device having row decoder supplying a negative potential to word lines during erase mode | Sumio Tanaka | 1997-10-21 |
| 5642072 | High voltage generator circuit | Junichi Miyamoto, Yasuo Itoh | 1997-06-24 |
| 5600592 | Nonvolatile semiconductor memory device having a word line to which a negative voltage is applied | Sumio Tanaka | 1997-02-04 |
| 5568419 | Non-volatile semiconductor memory device and data erasing method therefor | Masao Kuriyama, Hironori Banba, Akira Umezawa, Nobuaki Otsuka | 1996-10-22 |
| 5559737 | Nonvolatile semiconductor memory capable of simultaneously equalizing bit lines and sense lines | Sumio Tanaka, Masao Kuriyama | 1996-09-24 |
| 5513146 | Nonvolatile semiconductor memory device having a row decoder supplying a negative potential to word lines during erase mode | Sumio Tanaka | 1996-04-30 |
| 5438542 | Nonvolatile semiconductor memory device | Sumio Tanaka | 1995-08-01 |
| 5428571 | Data latch circuit having non-volatile memory cell equipped with common floating gate and stress relaxing transistor | Hironori Banba | 1995-06-27 |
| 5394077 | Internal power supply circuit for use in a semiconductor device | — | 1995-02-28 |
| 5392253 | Nonvolatile semiconductor memory device having row decoder supplying a negative potential to word lines during erase mode | Sumio Tanaka | 1995-02-21 |
| 5325328 | Sense amplifier output circuit used in semiconductor memory devices | Yukinori Muroya | 1994-06-28 |
| 5311470 | Data latch circuit having non-volatile memory cell | Hironori Banba | 1994-05-10 |
| 5295105 | Semiconductor memory device | — | 1994-03-15 |
| 5291045 | Non-volatile semiconductor memory device using a differential cell in a memory cell | — | 1994-03-01 |
| 5262919 | Semiconductor memory device including programming circuitry | Masao Kuriyama, Junichi Miyamoto | 1993-11-16 |
| 5253201 | Writing control circuit employed in non-volatile semiconductor memory device | Hironori Banba | 1993-10-12 |
| 5243569 | Differential cell-type EPROM incorporating stress test circuit | — | 1993-09-07 |