Issued Patents All Time
Showing 26–41 of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 4864164 | Integrated circuit with switching noise reduction by feedback | Shigeo Ohshima, Youichi Suzuki | 1989-09-05 |
| 4760560 | Random access memory with resistance to crystal lattice memory errors | Shoji Ariizumi, Shigeto Mizukami | 1988-07-26 |
| 4725746 | MOSFET buffer circuit with an improved bootstrapping circuit | Shoji Ariizumi | 1988-02-16 |
| 4673969 | Semiconductor device having multiple conductive layers and the method of manufacturing the semiconductor device | Shoji Ariizumi | 1987-06-16 |
| 4648075 | Redundancy circuit for a semiconductor memory device | Shoji Ariizumi | 1987-03-03 |
| 4578694 | Inverter circuit provided with gate protection | Shoji Ariizumi | 1986-03-25 |
| 4554469 | Static bootstrap semiconductor drive circuit | Shoji Ariizumi | 1985-11-19 |
| 4549102 | Driver circuit having a bootstrap buffer circuit | Shoji Ariizumi | 1985-10-22 |
| 4544941 | Semiconductor device having multiple conductive layers and the method of manufacturing the semiconductor device | Shoji Ariizumi | 1985-10-01 |
| 4541006 | Static memory having load polysilicon resistors formed over driver FET drains | Shoji Ariizumi | 1985-09-10 |
| 4539490 | Charge pump substrate bias with antiparasitic guard ring | Shoji Ariizumi | 1985-09-03 |
| 4535426 | Semiconductor memory device | Shoji Ariizumi, Fujio Masuoka | 1985-08-13 |
| 4504746 | Semiconductor buffer circuit using enhancement-mode, depletion-mode and zero threshold mode transistors | Shoji Ariizumi | 1985-03-12 |
| 4453175 | MOS Static RAM layout with polysilicon resistors over FET gates | Shoji Ariizumi | 1984-06-05 |
| 4399520 | Semiconductor integrated circuit device | Shoji Ariizumi, Hisaaki Maiwa, Seishi Okamoto | 1983-08-16 |
| 4384220 | MOS Transistor circuit with a power-down function | Shoji Ariizumi | 1983-05-17 |