Issued Patents All Time
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5617553 | Computer system which switches bus protocols and controls the writing of a dirty page bit of an address translation buffer | Takeshi Aikawa, Mitsuo Saito | 1997-04-01 |
| 5561774 | Parallel processing type processor system with trap and stall control functions | Takeshi Aikawa, Mitsuo Saito, Kenji Takeda | 1996-10-01 |
| 5446849 | Electronic computer which executes squash branching | Takeshi Aikawa, Mitsuo Saito | 1995-08-29 |
| 5377339 | Computer for simultaneously executing instructions temporarily stored in a cache memory with a corresponding decision result | Mitsuo Saito, Takeshi Aikawa | 1994-12-27 |
| 5371865 | Computer with main memory and cache memory for employing array data pre-load operation utilizing base-address and offset operand | Takeshi Aikawa, Mitsuo Saito | 1994-12-06 |
| 5276821 | Operation assignment method and apparatus therefor | Toru Imai, Takeshi Aikawa, Mitsuo Saito | 1994-01-04 |