KS

Keishi Sakanushi

KT Kabushiki Kaisha Toshiba: 3 patents #8,011 of 21,451Top 40%
OU Osaka University: 1 patents #681 of 1,984Top 35%
Overall (All Time): #1,209,981 of 4,157,543Top 30%
4
Patents All Time

Issued Patents All Time

Showing 1–4 of 4 patents

Patent #TitleCo-InventorsDate
9190150 Non-volatile memory device having 3D memory cell array with improved wordline and contact layout 2015-11-17
9166624 Error-correcting code processing method and device Masaharu Imai, Yoshinori Takeuchi, Takashi Hamabe, Kazuki Ohya, Masaaki Abe 2015-10-20
9158878 Method and apparatus for generating circuit layout using design model and specification 2015-10-13
8972907 Layout correcting method, recording medium and design layout correcting apparatus Yoko Yokoyama, Chikaaki Kodama 2015-03-03