Issued Patents All Time
Showing 51–70 of 70 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8433882 | Disk array control device and storage device | Takehiko Kurashige | 2013-04-30 |
| 8429333 | Memory system with efficient data search processing | Kosuke Hatsuda, Hidenori Matsuzaki | 2013-04-23 |
| 8407402 | Memory system and data erasing method therefor | Hidenori Matsuzaki, Kosuke Hatsuda | 2013-03-26 |
| 8285954 | Memory system managing a plurality of logs | Hidenori Matsuzaki, Kosuke Hatsuda, Toshikatsu Hida | 2012-10-09 |
| 8276043 | Memory system | Hidenori Matsuzaki, Kosuke Hatsuda, Hiroki Matsudaira | 2012-09-25 |
| 8225047 | Memory system with pre-fetch operation | Hidenori Matsuzaki, Kosuke Hatsuda | 2012-07-17 |
| 8219861 | Semiconductor storage device | Toshikatsu Hida, Shinichi Kanno, Hirokuni Yano, Kazuya Kitsunai, Shigehiro Asano | 2012-07-10 |
| 8209471 | Memory system | Kosuke Hatsuda, Hidenori Matsuzaki | 2012-06-26 |
| 8190812 | Memory system capable of restoring broken information | Hidenori Matsuzaki, Kosuke Hatsuda | 2012-05-29 |
| 8176237 | Solid state drive with input buffer | Hidenori Matsuzaki, Kosuke Hatsuda | 2012-05-08 |
| 8171208 | Memory system | Hidenori Matsuzaki, Kosuke Hatsuda | 2012-05-01 |
| 8108593 | Memory system for flushing and relocating data | Hidenori Matsuzaki, Kosuke Hatsuda, Wataru Okamoto, Ryoichi Kato | 2012-01-31 |
| 8108594 | Memory system | Hidenori Matsuzaki, Kosuke Hatsuda, Hiroki Matsudaira | 2012-01-31 |
| 8060797 | Semiconductor storage device | Toshikatsu Hida, Shinichi Kanno, Hirokuni Yano, Kazuya Kitsunai, Shigehiro Asano | 2011-11-15 |
| 8015347 | Memory system and control method thereof | Kazuya Kitsunai, Shinichi Kanno, Hirokuni Yano, Toshikatsu Hida | 2011-09-06 |
| 7978698 | Terminal for performing multiple access transmission suitable to a transmission path having varied characteristics | Tsuyoshi Yamaguchi, Yuji Igata, Yasushi Yokomitsu, Toru Yasukawa, Shinichiro Ohmi +3 more | 2011-07-12 |
| 7958411 | Memory system and control method thereof | Shinichi Kanno, Hirokuni Yano, Toshikatsu Hida, Kazuya Kitsunai | 2011-06-07 |
| 7949910 | Memory system and control method thereof | Shinichi Kanno, Hirokuni Yano, Toshikatsu Hida, Kazuya Kitsunai | 2011-05-24 |
| 7904640 | Memory system with write coalescing | Hidenori Matsuzaki, Kosuke Hatsuda | 2011-03-08 |
| 5194764 | Data output buffer circuit for semiconductor integrated circuit having output buffers with different delays | Tsukasa Miyawaki, Masami Atoh, Masakazu Gotou, Masakazu Iwashita, Michio Kaji | 1993-03-16 |