HK

Hiromasa Kaida

KT Kabushiki Kaisha Toshiba: 2 patents #9,982 of 21,451Top 50%
Overall (All Time): #2,184,036 of 4,157,543Top 55%
2
Patents All Time

Issued Patents All Time

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
6951007 Wire layout design apparatus and method for integrated circuits — 2005-09-27
5222031 Logic cell placement method for semiconductor integrated circuit — 1993-06-22