Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12125542 | Semiconductor memory device | Wataru MORIYAMA, Hayato KONNO, Takao Nakajima, Masaki Fujiu, Kiyoaki Iwasa +1 more | 2024-10-22 |
| 11917826 | Semiconductor memory device with three-dimensional memory cells | — | 2024-02-27 |
| 11430805 | Semiconductor memory device including three-dimensional memory cell arrays | — | 2022-08-30 |
| 10672794 | Semiconductor memory device including three-dimensional memory cell arrays | — | 2020-06-02 |
| 10332907 | Semiconductor memory device with three-dimensional memory cells | — | 2019-06-25 |
| 9929173 | Method of controlling a semiconductor memory device | — | 2018-03-27 |
| 9508740 | 3D stacked semiconductor memory architecture with conductive layer arrangement | — | 2016-11-29 |
| 9281016 | 3D stacked semiconductor memory devices with sense amplifier electrically connected to a selecting circuit | — | 2016-03-08 |
| 8873330 | Semiconductor memory device | Kiyotaro Itagaki | 2014-10-28 |
| 8817512 | Semiconductor memory device | — | 2014-08-26 |
| 8804420 | Semiconductor memory device | — | 2014-08-12 |
| 8787061 | Semiconductor memory device | — | 2014-07-22 |
| 8416605 | Non-volatile semiconductor storage device | — | 2013-04-09 |
| 8406036 | Semiconductor memory device | — | 2013-03-26 |
| 8391052 | Nonvolatile semiconductor memory device | — | 2013-03-05 |
| 8184501 | Systems and methods for stretching clock cycles in the internal clock signal of a memory array macro | — | 2012-05-22 |
| 8144500 | Semiconductor memory device | — | 2012-03-27 |
| 7940544 | Memory system having multiple vias at junctions between traces | — | 2011-05-10 |
| 7733717 | Memory system having distributed read access delays | — | 2010-06-08 |