Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11463720 | Functional safety method, system, and corresponding computer program product | Nicola Marinelli | 2022-10-04 |
| 11436162 | Functional safety method, corresponding system-on-chip, device and vehicle | Denis Dutey, Om Ranjan | 2022-09-06 |
| 11055173 | Redundant storage of error correction code (ECC) checkbits for validating proper operation of a static random access memory (SRAM) | Om Ranjan, Denis Dutey | 2021-07-06 |
| 10860415 | Memory architecture including response manager for error correction circuit | Om Ranjan, Abhishek Gupta | 2020-12-08 |
| 10528422 | Redundant storage of error correction code (ECC) checkbits for validating proper operation of a static random access memory (SRAM) | Om Ranjan, Denis Dutey | 2020-01-07 |
| 10379937 | Memory architecture including response manager for error correction circuit | Om Ranjan, Abhishek Gupta | 2019-08-13 |
| 9203725 | Update of a cumulative residence time of a packet in a packet-switched communication network | Luigi Ronchetti, Giorgio Cazzaniga, Carlo Costantini | 2015-12-01 |
| 9154446 | Device and method for switching data traffic in a digital transmission network | Luigi Ronchetti, Andrea Paparella, Vincenzo Sestito | 2015-10-06 |
| 8594136 | Transmission of parallel data flows on a parallel bus | Silvio Cucchi, Luigi Ronchetti | 2013-11-26 |
| 8429511 | Equipment protection method and apparatus | Silvio Cucchi, Giuseppe Badalucco, Carlo Costantini, Luigi Ronchetti | 2013-04-23 |
| 7289502 | Method and device for routing or compressing packets destination address containing classless address | Marco Pavesi, Salvatore Matteo Crudo | 2007-10-30 |
| 7130942 | Interface bus protocol for managing transactions in a system of distributed microprocessor interfaces toward marco-cell based designs implemented as ASIC or FPGA bread boarding | Marco Pavesi, Giuseppe De Blasio | 2006-10-31 |
| 7082563 | Automated method for generating the cyclic redundancy check for transmission of multi-protocol packets | Maurizio Corradini, Giacomo Accattoli | 2006-07-25 |
| 7036095 | Clock generation system for a prototyping apparatus | Marco Pavesi, Maurizio Grassi, Fabio De Pieri, Mauro Ferloni | 2006-04-25 |
| 6970966 | System of distributed microprocessor interfaces toward macro-cell based designs implemented as ASIC or FPGA bread boarding and relative common bus protocol | Marco Pavesi, Giuseppe De Blasio | 2005-11-29 |
| 6964574 | Daughter board for a prototyping system | Marco Pavesi, Fabio De Pieri, Maurizo Grassi, Mauro Ferloni | 2005-11-15 |
| 6549536 | Method of address compression for cell-based and packet-based protocols and hardware implementations thereof | Marco Pavesi | 2003-04-15 |