Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
WL

Wee Liew — 8 Patents

LSLsi: 7 patents #535 of 3,238Top 20%
Intel: 1 patents #18,326 of 30,777Top 60%
San Jose, CA: #7,707 of 32,062 inventorsTop 25%
California: #74,834 of 386,348 inventorsTop 20%
Overall (All Time): #600,572 of 4,157,543Top 15%
8 Patents All Time
Wee Liew has been granted 8 US patents. The first was granted in 2003 and the most recent in December 2024. Wee Liew ranks #600,572 of 4,157,543 US inventors in our database (top 14.4%). Patent records list Wee Liew in San Jose, CA, US.

Patents per Year

Patents granted per year, 2003 to 2024Bar chart with a peak of 4 patents in 2003.peak 42003: 4 patents20032004: 2 patents20042005: 1 patents20052024: 1 patents2024

Issued Patents All Time

Showing 1–8 of 8 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12182047 Chip-to-chip interface of a multi-chip module (MCM) Kameran Azadet, Ramani Tatikola, Edwin Thaller, Patrick Torta, Yu Wang +2 more 2024-12-31 $16,542,000
6897555 Integrated circuit package and method for a PBGA package having a multiplicity of staggered power ring segments for power connection to integrated circuit die Hong T. Lim, Chengyu Guo 2005-05-24 $2,787,000
6825554 PBGA electrical noise isolation of signal traces Aritharan Thurairajaratnam, Nadeem HAQUE 2004-11-30 $3,527,000
6687133 Ground plane on 2 layer PBGA Hong T. Lim, Chengyu Guo 2004-02-03 $4,995,000
6608376 Integrated circuit package substrate with high density routing mechanism Aritharan Thurairajaratnam, Maniam Alagaratnam 2003-08-19 $10,855,000
6566167 PBGA electrical noise isolation of signal traces Aritharan Thurairajaratnam, Nadeem HAQUE 2003-05-20 $2,301,000
6525421 Molded integrated circuit package Chok J. Chia, Seng-Sooi Lim 2003-02-25 $3,351,000
6512293 Mechanically interlocking ball grid array packages and method of making Chok J. Chia, Seng-Sooi Lim 2003-01-28 $3,469,000