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Paralleizing loops in the presence of possible memory aliases |
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Processor architecture and method for simplifying programming single instruction, multiple data within a register |
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2017-01-31 |
| 9460016 |
Cache way prediction |
John Redford |
2016-10-04 |
| 9342306 |
Predicate counter |
Andrew J. Higham, Boris Lerner, Kaushal Sanghai, John Redford, Michael S. Allen |
2016-05-17 |
| 9201828 |
Memory interconnect network architecture for vector processor |
Kaushal Sanghai, Boris Lerner, John Redford |
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| 9038042 |
Staged loop instructions |
Andrew J. Higham |
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| 6795485 |
Integrated QPSK/FSK demodulator |
— |
2004-09-21 |
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Method and apparatus for effecting seamless data rate changes in a video compression system |
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2001-02-13 |
| 5861919 |
Dynamic rate optimization for an ensemble of video encoders |
David Arnstein |
1999-01-19 |
| 5859660 |
Non-seamless splicing of audio-video transport streams |
William L. Helms |
1999-01-12 |
| 5828414 |
Reduction of timing jitter in audio-video transport streams |
Thomas Duncan Lookabaugh |
1998-10-27 |
| 5717464 |
Rate control for a video encoder |
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1998-02-10 |
| 5420639 |
Rate adaptive huffman coding |
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1995-05-30 |