WP

Wladimir Plagges

SY Synopsys: 1 patents #1,143 of 2,302Top 50%
📍 Santiago, CL: #295 of 1,142 inventorsTop 30%
Overall (All Time): #2,550,522 of 4,157,543Top 65%
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Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
12158770 Power-efficient enable signal for fanin-based sequential clock gating on enabled flip flops Muzaffer Hiraoglu, Esteban Osses 2024-12-03