Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12218677 | Circuit and method for calibration of digital-to-analog converter | Jan Mulder, Mohammadreza Mehrpoo, Sijia Wang | 2025-02-04 |
| 12184296 | Systems and method of compensating for nonlinear capacitance in converters | Jan Mulder, Mohammadreza Mehrpoo, Sijia Wang | 2024-12-31 |
| 12143120 | Systems and methods of signed conversion | Jan Mulder, Mohammadreza Mehrpoo, Sijia Wang | 2024-11-12 |
| 12113542 | Calibration detector with two offset compensation loops | Jan Mulder, Mohammadreza Mehrpoo, Sijia Wang, Jeffrey Allan Riley | 2024-10-08 |
| 10020829 | Method and apparatus to avoid noise figure degradation of a wireless receiver by a blocker | — | 2018-07-10 |
| 9614662 | Multi-input wireless receiver based on RF sampling techniques | Jiangfeng Wu, David Garrett | 2017-04-04 |
| 9077355 | Switched capacitance converter | — | 2015-07-07 |
| 9031177 | Digital calibration of analog distortion using split analog front-end | Jan Roelof Westra | 2015-05-12 |
| 8749410 | Calibration of interleaving errors in a multi-lane analog-to-digital converter | Christopher M. Ward, Klaas Bult | 2014-06-10 |
| 8674866 | Interleaved return-to-zero, high performance digital-to-analog converter | Christopher M. Ward | 2014-03-18 |
| 8598906 | Low-power ethernet transmitter | Christopher M. Ward, Jan Mulder, Ovidiu Bajdechi | 2013-12-03 |
| 8446184 | Mode dependent driving of the center tap in ethernet communications | Christopher M. Ward, Ovidiu Bajdechi, Erol Arslan | 2013-05-21 |
| 8325756 | Method and system for a power reduction scheme for Ethernet PHYs | Mark Berman, Manolito Catalasan, Ovidiu Bajdechi, Christopher M. Ward, Bruce Conway +1 more | 2012-12-04 |
| 7545296 | Interleaved track and hold circuit | Klaas Bult | 2009-06-09 |