| 11023360 |
Systems and methods for configuring programmable logic devices for deep learning networks |
Girish Venkataramani, Wang Chen, Bharathi Yogaraj, Yuteng Zhou, Vibha Patil +2 more |
2021-06-01 |
| 10423733 |
Systems and methods for sharing resources having different data types |
Girish Venkataramani, Rama Kokku, Sanmukh Rao Kuppannagari |
2019-09-24 |
| 10261760 |
Systems and methods for tracing performance information from hardware realizations to models |
— |
2019-04-16 |
| 10095814 |
User-constrained delay redistribution |
Partha Biswas, Zhihong Zhao |
2018-10-09 |
| 10078717 |
Systems and methods for estimating performance characteristics of hardware implementations of executable models |
Girish Venkataramani, Rama Kokku |
2018-09-18 |
| 9846571 |
Utilizing clock rate pipelining to generate code for multi-rate systems |
Girish Venkataramani, Wang Chen |
2017-12-19 |
| 9817931 |
Systems and methods for generating optimized hardware descriptions for models |
Girish Venkataramani, Rama Kokku |
2017-11-14 |
| 9779195 |
Model-based retiming with functional equivalence constraints |
Girish Venkataramani |
2017-10-03 |
| 9355000 |
Model level power consumption optimization in hardware description generation |
Partha Biswas, Zhihong Zhao, Wang Chen |
2016-05-31 |
| 8990739 |
Model-based retiming with functional equivalence constraints |
Girish Venkataramani |
2015-03-24 |