Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11790049 | Techniques for improving machine-learning accuracy and convergence | Gaurav Dhir, Ankit Sirmorya | 2023-10-17 |
| 10852956 | Structure of a high-bandwidth-memory command queue of a memory controller with external per-bank refresh and burst reordering | Xiaofei Li, Yanjuan Zhan, Zhehong Qian, Buying Du | 2020-12-01 |
| 10579303 | Memory controller having command queue with entries merging | Xiaofei Li, Zhehong Qian, Buying Du | 2020-03-03 |
| 10409357 | Command-oriented low power control method of high-bandwidth-memory system | Xiaofei Li, Zhehong Qian, Yanjuan Zhan, Buying Du | 2019-09-10 |
| 10162522 | Architecture of single channel memory controller to support high bandwidth memory of pseudo channel mode or legacy mode | Xiaofei Li, Zhehong Qian, Yanjuan Zhan, Buying Du | 2018-12-25 |
| 9881664 | Per-group delay line architecture to de-skew input/output timing between a high bandwidth memory (HBM) physical (PHY) interface and the HBM device | Guangxi Ying, Yanjuan Zhan, Zhehong Qian | 2018-01-30 |
| 7716621 | Method and system for improving signal integrity in integrated circuit designs | Chih-Wei Chang, Louis Chao, So-Zen Yao | 2010-05-11 |
| 5974245 | Method and apparatus for making integrated circuits by inserting buffers into a netlist | Sunil Ashtaputre, Jacob Greidinger, Mark R. Hartoog, Moazzem Hossain, Siu-Tong Hui | 1999-10-26 |
| 5666290 | Interactive time-driven method of component placement that more directly constrains critical paths using net-based constraints | Sunil Ashtaputre | 1997-09-09 |
| 5638291 | Method and apparatus for making integrated circuits by inserting buffers into a netlist to control clock skew | Sunil Ashtaputre, Jacob Greidinger, Mark R. Hartoog, Moazzem Hossain, Siu-Tong Hui | 1997-06-10 |