Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10347501 | Enhanced patterning of integrated circuit layer by tilted ion implantation | Xi Zhang, Peng Zheng | 2019-07-09 |
| 9355860 | Method for achieving uniform etch depth using ion implantation and a timed etch | — | 2016-05-31 |
| 8686497 | DRAM cell utilizing a doubly gated vertical channel | Wookhyun Kwon | 2014-04-01 |
| 8592109 | Patterning a single integrated circuit layer using automatically-generated masks and multiple masking layers | — | 2013-11-26 |
| 8399183 | Patterning a single integrated circuit layer using automatically-generated masks and multiple masking layers | — | 2013-03-19 |
| 8043943 | Low-temperature formation of polycrystalline semiconductor films via enhanced metal-induced crystallization | Roya Maboudian, Frank W. DelRio, Joanna Lai | 2011-10-25 |
| 7995380 | Negative differential resistance pull up element for DRAM | — | 2011-08-09 |
| 7807523 | Sequential selective epitaxial growth | Qiang Lu | 2010-10-05 |
| 7710771 | Method and apparatus for capacitorless double-gate storage | Charles C. Kuo | 2010-05-04 |
| 7605449 | Enhanced segmented channel MOS transistor with high-permittivity dielectric isolation material | Qiang Lu | 2009-10-20 |
| 7560201 | Patterning a single integrated circuit layer using multiple masks and multiple masking layers | — | 2009-07-14 |
| 7508031 | Enhanced segmented channel MOS transistor with narrowed base regions | Qiang Lu | 2009-03-24 |
| 7494933 | Method for achieving uniform etch depth using ion implantation and a timed etch | — | 2009-02-24 |