Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10672720 | Semiconductor device and method of producing semiconductor device | Tomoyuki Yamada, Fumio Ushida, Shigetoshi Takeda, Koji Banno, Takayoshi Minami | 2020-06-02 |
| 10147687 | Semiconductor device and method of producing semiconductor device | Tomoyuki Yamada, Fumio Ushida, Shigetoshi Takeda, Koji Banno, Takayoshi Minami | 2018-12-04 |
| 9881878 | Semiconductor device and method of producing semiconductor device | Tomoyuki Yamada, Fumio Ushida, Shigetoshi Takeda, Koji Banno, Takayoshi Minami | 2018-01-30 |
| 9824981 | Semiconductor device and method of producing semiconductor device | Tomoyuki Yamada, Fumio Ushida, Shigetoshi Takeda, Koji Banno, Takayoshi Minami | 2017-11-21 |
| 8928396 | Electronic circuit and semiconductor device | Jun Nagayama | 2015-01-06 |
| 8514638 | Write control circuit and semiconductor device | Tsuyoshi Koyashiki, Jun Nagayama, Masahito Isoda | 2013-08-20 |
| 8193614 | Semiconductor device, moisture-resistant frame, groove and method of producing semiconductor device | Tomoyuki Yamada, Fumio Ushida, Shigetoshi Takeda, Koji Banno, Takayoshi Minami | 2012-06-05 |
| 7673266 | Timing analysis method and apparatus, computer-readable program and computer-readable storage medium | Masamichi Kamiyama | 2010-03-02 |
| 5576996 | Semiconductor memory device having a variably write pulse width capability | Masaya Sugimoto | 1996-11-19 |
| 4796233 | Bipolar-transistor type semiconductor memory device having redundancy configuration | Isao Fukushi | 1989-01-03 |
| 4783781 | Semiconductor memory device having redundancy configuration with read circuit for defective memory address | — | 1988-11-08 |
| 4757475 | Semiconductor memory device having diode matrix type decoder and redundancy configuration | — | 1988-07-12 |
| 4745582 | Bipolar-transistor type random access memory device having redundancy configuration | Isao Fukushi | 1988-05-17 |
| 4740918 | Emitter coupled semiconductor memory device having a low potential source having two states | Yoshinori Okajima | 1988-04-26 |