Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7131086 | Logic verification device, logic verification method and logic verification computer program | Junya Yamasaki, Kenya Takeyama, Yukio Makino | 2006-10-31 |
| 5856925 | Method for making electronic circuit design data and CAD system using the method | Hisataka Fukase | 1999-01-05 |