| 8270322 |
Method and system for arbitrating data transmissions |
Almir Davis, Jeffrey Kinne, Christopher S. MacLellan |
2012-09-18 |
| 7574555 |
Memory system having daisy chained memory controllers |
Ofer Porat, Brian K. Campbell, Brian D. Magnuson |
2009-08-11 |
| 7400672 |
Method and system for detecting transmitter errors |
Almir Davis, Jeffrey Kinne, Christopher S. MacLellan |
2008-07-15 |
| 7383492 |
First-in/first-out (FIFO) information protection and error detection method and apparatus |
Philip M. Sailer, Nicholas Paluzzi, Avinash Kallat, Krzysztof Dobecki |
2008-06-03 |
| 7337250 |
Low latency data transmission method and system |
Almir Davis, Jeffrey Kinne, Christopher S. MacLellan |
2008-02-26 |
| 7099971 |
Arbitration system |
Nicholas Paluzzi, Philip M. Sailer |
2006-08-29 |
| 7073031 |
Multi-processor system having data coherency |
Christopher S. MacLellan, Avinash Kallat, Almir Davis |
2006-07-04 |
| 6915475 |
Data integrity management for data storage systems |
Victor Tung |
2005-07-05 |
| 6880032 |
Data storage system having concurrent ESCON channels |
Kenneth Mark SULLIVAN |
2005-04-12 |
| 6839782 |
Computer storage system incorporating on-board EEPROMS containing product data |
Victor Tung, Rudy M. Bauer |
2005-01-04 |
| 6742146 |
Techniques for providing data within a data storage system |
William Gross, Victor Tung |
2004-05-25 |
| 6738842 |
System having plural processors and a uni-cast/broadcast communication arrangement |
Rudy M. Bauer, Victor Tung, Brian Arsenault |
2004-05-18 |
| 6643722 |
Data storage system having director boards with plural processors |
Kenneth Mark SULLIVAN, Rudy M. Bauer |
2003-11-04 |
| 6578128 |
Address management for a shared memory region on a multi-processor controller board |
Brian Arsenault |
2003-06-10 |
| 6560573 |
Storage controller with hardware emulation controller for emulation between control processor and transfer circuitry compatible to different processor |
Victor Tung, Paul C. Wilson, Rudy M. Bauer |
2003-05-06 |
| 6467047 |
Computer storage system controller incorporating control store memory with primary and secondary data and parity areas |
Victor Tung, Rudy M. Bauer |
2002-10-15 |
| 5890207 |
High performance integrated cached storage device |
Gal Sne, Victor Tung |
1999-03-30 |
| 5890219 |
Redundant writing of data to cached storage system |
Gal Sne, Victor Tung |
1999-03-30 |
| 5884055 |
Method and apparatus including a shared resource and multiple processors running a common control program accessing the shared resource |
Victor Tung, Gal Sne |
1999-03-16 |