SD

Steve Durrill

CS Cadence Design Systems: 4 patents #399 of 2,263Top 20%
📍 San Jose, CA: #12,320 of 32,062 inventorsTop 40%
🗺 California: #124,610 of 386,348 inventorsTop 35%
Overall (All Time): #1,219,615 of 4,157,543Top 30%
4
Patents All Time

Issued Patents All Time

Showing 1–4 of 4 patents

Patent #TitleCo-InventorsDate
8898039 Physical topology-driven logical design flow Taranjit Singh Kukal, Nikhil Gupta, Vikrant Khanna, Dingru Xiao 2014-11-25
8732651 Logical design flow with structural compatability verification Taranjit Singh Kukal, Nikhil Gupta, Vikrant Khanna, Dingru Xiao 2014-05-20
8271933 Pin unspecific device planning for printed circuit board layout Vikas Kohli, Dhamarajan Sankaran 2012-09-18
7168041 Method and apparatus for table and HDL based design entry Vikas Kohli 2007-01-23