SY

Shin-te Yang

GL Genesys Logic: 2 patents #18 of 66Top 30%
Overall (All Time): #2,068,984 of 4,157,543Top 50%
2
Patents All Time

Issued Patents All Time

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
8407508 Serial bus clock frequency calibration system and method thereof Wei-Te Lee, Wen-Ming Huang 2013-03-26
8140882 Serial bus clock frequency calibration system and method thereof Wei-Te Lee, Yen-fah Chu 2012-03-20