Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7062637 | DSP operations with permutation of vector complex data type operands | Kumar Ganapathy | 2006-06-13 |
| 6988184 | Dyadic DSP instruction predecode signal selective multiplexing data from input buses to first and second plurality of functional blocks to execute main and sub operations | Kumar Ganapathy | 2006-01-17 |
| 6842845 | Methods and apparatuses for signal processing | Kumar Ganapathy | 2005-01-11 |
| 6842850 | DSP data type matching for operation using multiple functional units | Kumar Ganapathy | 2005-01-11 |
| 6832306 | Method and apparatus for a unified RISC/DSP pipeline controller for both reduced instruction set computer (RISC) control instructions and digital signal processing (DSP) instructions | Kumar Ganapathy | 2004-12-14 |
| 6772319 | Dyadic instruction processing instruction set architecture with 20-bit and 40-bit DSP and control instructions | Kumar Ganapathy | 2004-08-03 |
| 6766446 | Method and apparatus for loop buffering digital signal processing instructions | Kumar Ganapathy, Kenneth Malich | 2004-07-20 |
| 6748516 | Method and apparatus for instruction set architecture to perform primary and shadow digital signal processing sub-instructions simultaneously | Kumar Ganapathy | 2004-06-08 |
| 6643768 | Dyadic DSP instruction processor with main and sub-operation functional blocks selected from each set of multiplier and adder | Kumar Ganapathy | 2003-11-04 |
| 6631461 | Dyadic DSP instructions for digital signal processors | Kumar Ganapathy | 2003-10-07 |
| 6598155 | Method and apparatus for loop buffering digital signal processing instructions | Kumar Ganapathy, Kenneth Malich | 2003-07-22 |
| 6557096 | Processors with data typer and aligner selectively coupling data bits of data buses to adder and multiplier functional blocks to execute instructions with flexible data types | Kumar Ganapathy | 2003-04-29 |
| 6446195 | Dyadic operations instruction processor with configurable functional blocks | Kumar Ganapathy | 2002-09-03 |
| 6408376 | Method and apparatus for instruction set architecture to perform primary and shadow digital signal processing sub-instructions simultaneously | Kumar Ganapathy | 2002-06-18 |
| 6330660 | Method and apparatus for saturated multiplication and accumulation in an application specific signal processor | Kumar Ganapathy | 2001-12-11 |