Issued Patents All Time
Showing 25 most recent of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7996805 | Method of stitching scan flipflops together to form a scan chain with a reduced wire length | — | 2011-08-09 |
| 7978454 | ESD structure that protects against power-on and power-off ESD event | — | 2011-07-12 |
| 7863962 | High voltage CMOS output buffer constructed from low voltage CMOS transistors | — | 2011-01-04 |
| 7723792 | Floating diodes | — | 2010-05-25 |
| 7633311 | PECL/LVPECL input buffer that employs positive feedback to provide input hysteresis, symmetric headroom, and high noise immunity | — | 2009-12-15 |
| 7518419 | Wideband power-on reset circuit | — | 2009-04-14 |
| 7424507 | High speed, low power, pipelined zero crossing detector that utilizes carry save adders | — | 2008-09-09 |
| 7388414 | Wideband power-on reset circuit with glitch-free output | — | 2008-06-17 |
| 7265599 | Flipflop that can tolerate arbitrarily slow clock edges | — | 2007-09-04 |
| 7260808 | Method and metric for low power standard cell logic synthesis | — | 2007-08-21 |
| 7185042 | High speed, universal polarity full adder which consumes minimal power and minimal area | — | 2007-02-27 |
| 7109747 | Low power, high speed logic controller that implements thermometer-type control logic by utilizing scan flip-flops and a gated clock | — | 2006-09-19 |
| 7098706 | High speed synchronizer for simultaneously initializing rising edge triggered and falling edge triggered flip-flops | — | 2006-08-29 |
| 7042267 | Gated clock circuit with a substantially increased control signal delay | — | 2006-05-09 |
| 7038898 | ESD protection circuit that can tolerate a negative input voltage during normal (non-ESD) operation | — | 2006-05-02 |
| 6981013 | Low power, minimal area tap multiplier | — | 2005-12-27 |
| 6977420 | ESD protection circuit utilizing floating lateral clamp diodes | — | 2005-12-20 |
| 6710432 | Integrated circuit package with low inductance ground path and improved thermal capability | — | 2004-03-23 |
| 6690555 | Electrostatic discharge protection circuit with cascoded trigger-switch suitable for use with over-voltage tolerant CMOS input/output buffers | — | 2004-02-10 |
| 6492855 | Flip flop which has complementary, symmetric, minimal timing skew outputs | — | 2002-12-10 |
| 6489825 | High speed, low power, minimal area double edge triggered flip flop | — | 2002-12-03 |
| 6397374 | Zero hold time circuit for high speed bus applications | — | 2002-05-28 |
| 6380770 | Low ground bounce and low power supply bounce output driver with dual, interlocked, asymmetric delay lines | — | 2002-04-30 |
| 6184729 | Low ground bounce and low power supply bounce output driver | — | 2001-02-06 |
| 6160428 | Universal on-chip initialization circuit | — | 2000-12-12 |