Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11595028 | Frequency doubler with duty cycle correction | Masoud Moslehi Bajestan, Marco Zanuso, Hasnain Lakdawala | 2023-02-28 |
| 11411569 | Calibration of sampling-based multiplying delay-locked loop (MDLL) | Masoud Moslehi Bajestan, Marco Zanuso, Hasnain Lakdawala | 2022-08-09 |
| 9032354 | Scan chain modification for reduced leakage | — | 2015-05-12 |
| 8453098 | Scan chain modification for reduced leakage | — | 2013-05-28 |
| 8203475 | Parallel mash ΔΣ modulator | Andras Pozsgay | 2012-06-19 |
| 7571402 | Scan chain modification for reduced leakage | — | 2009-08-04 |
| 7337419 | Crosstalk noise reduction circuit and method | — | 2008-02-26 |
| 7301372 | Domino logic compatible scannable flip-flop | Scott B. Anderson, Thomas Zounes | 2007-11-27 |
| 7254796 | Method for synthesizing domino logic circuits cross reference to related patent application using partition | Fabrizio Viglione, Bernard Bourgin | 2007-08-07 |
| 7002374 | Domino logic compatible scannable flip-flop | Scott B. Anderson, Thomas Zounes | 2006-02-21 |
| 6954909 | Method for synthesizing domino logic circuits | Fabrizio Viglione, Bernard Bourgin | 2005-10-11 |
| 6911845 | Pulse triggered static flip-flop having scan test | Marco Cavalli | 2005-06-28 |
| 6820109 | System and method for predictive comparator following addition | Lun Bin Huang | 2004-11-16 |
| 6729168 | Circuit for determining the number of logical one values on a data bus | — | 2004-05-04 |
| 6665691 | Circuit for detecting numbers equal to a power of two on a data bus | — | 2003-12-16 |
| 6366944 | Method and apparatus for performing signed/unsigned multiplication | Jeffrey C. Herbert | 2002-04-02 |
| 6195672 | Saturation detection in floating point to integer conversions | Jason F. Gouger, Jeffrey C. Herbert | 2001-02-27 |
| 6148315 | Floating point unit having a unified adder-shifter design | Jeffrey C. Herbert, Roland A. Bechade | 2000-11-14 |
| 6148316 | Floating point unit equipped also to perform integer addition as well as floating point to integer conversion | Jeffrey C. Herbert, Jason F. Gouger | 2000-11-14 |
| 6134576 | Parallel adder with independent odd and even sum bit generation cells | Roland A. Bechade, Jeffrey C. Herbert | 2000-10-17 |