Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10713388 | Stacked encryption | Michael James Shull | 2020-07-14 |
| 9545289 | Systems and methods for endoluminal valve creation | Fletcher T. Wilson, Rhunjay James Yu, Pedram Afshar | 2017-01-17 |
| 7653673 | Efficient method for identifying few largest differences from a list of numbers | Himanshu Agrawal | 2010-01-26 |
| 7647571 | Method of identifying state nodes at the transistor level in a sequential digital circuit | Tathagato Rai Dastidar, Amir Yashfe | 2010-01-12 |
| 7581199 | Use of state nodes for efficient simulation of large digital circuits at the transistor level | Tathagato Rai Dastidar, Amir Yashfe | 2009-08-25 |
| 7490279 | Test interface for random access memory (RAM) built-in self-test (BIST) | Rahul Kumar, Suryanarayana R. Maturi | 2009-02-10 |
| 7412695 | Transient state nodes and a method for their identification | Tathagato Rai Dastidar, Amir Yashfe | 2008-08-12 |
| 7333924 | Method and system for device level simulation of large semiconductor memories and other circuits | Tathagato Rai Dastidar | 2008-02-19 |
| 7254791 | Method of measuring test coverage of backend verification runsets and automatically identifying ways to improve the test suite | Himanshu Agrawal, Tathagato Rai Dastidar | 2007-08-07 |
| 7246334 | Topological analysis based method for identifying state nodes in a sequential digital circuit at the transistor level | Tathagato Rai Dastidar | 2007-07-17 |
| 7216307 | Method of identifying state nodes at the transistor level in a sequential digital circuit using minimum combinatorial feedback loop | Tathagato Rai Dastidar, Amir Yashfe | 2007-05-08 |
| 6643832 | Virtual tree-based netlist model and method of delay estimation for an integrated circuit design | Mikhail I. Grinchuk, Pedja Raspopovic | 2003-11-04 |