Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12316731 | Device with low-power synchronizing circuitry and related method | Ankur Bal, Rajnish Garg, Rohit Gupta | 2025-05-27 |
| 7774682 | Processing configuration data frames | Ashish Goel, Davinder Aggarwal | 2010-08-10 |
| 7606969 | Programmable logic devices | Davinder Aggarwal, Ashish Goel | 2009-10-20 |
| 7350134 | Method and apparatus of reloading erroneous configuration data frames during configuration of programmable logic devices | Ashish Goel, Davinder Aggarwal | 2008-03-25 |
| 7154299 | Architecture for programmable logic device | Parvesh Swami, Deepak Agarwal | 2006-12-26 |
| 7109749 | Programmable logic devices providing reduced power consumption | Parvesh Swami, Deepak Agarwal | 2006-09-19 |
| 7030648 | High performance interconnect architecture for field programmable gate arrays | Ankur Bal | 2006-04-18 |
| 6879185 | Low power clock distribution scheme | Parvesh Swami, Deepak Agarwal | 2005-04-12 |